Field-Effect (FET) transistors
References: Hayes & Horowitz (pp 142-162 and 244-266),
Rizzoni (chapters 8 & 9)
In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and,
therefore, its current-carrying capability, is varied by the application of an electric field (thus,
the name field-effect transistor). As such, a FET is a “voltage-controlled” device. The most
widely used FETs are Metal-Oxide-Semiconductor FETs (or MOSFET). MOSFET can be
manufactured as enhancement-type or depletion-type MOSFETs. Another type of FET is
the Junction Field-Effect Transistors (JFET) which is not based on metal-oxide fabrication
technique. FETs in each of these three categories can be fabricated either as a n-channel
device or a p-channel device. As transistors in these 6 FET categories behave in a very
similar fashion, we will focus below on the operation of enhancement MOSFETs that are
the most popular.
n-Channel Enhancement-Type MOSFET (NMOS)
The physical structure of a n-Channel Enhancement-Type MOSFET (NMOS) is shown.
The device is fabricated on a p-type substrate (or Body). Two heavily doped n-type regions (Source and Drain) are created in the substrate. A thin (fraction of micron) layer
of SiO2 , which is an excellent electrical insulator, is deposited between source and drain
region. Metal is deposited on the insulator to form the Gate of the device (thus, metal-oxide
semiconductor). Metal contacts are also made to the source, drain, and body region.
To see the operation of a NMOS, let’s ground the source and the body and apply a voltage
vGS between the gate and the source, as is shown above. This voltage repels the holes in
the p-type substrate near the gate region, lowering the concentration of the holes. As v GS
increases, hole concentration decreases, and the region near gate behaves progressively more
like intrinsic semiconductor material (excess hole concentration zero) and then, finally, like
ECE60L Lecture...