INTERNATIONAL
JOURNAL OF
ENGINEERING,
SCIENCE AND
TECHNOLOGY
www.ijest-ng.com
International Journal of Engineering, Science and Technology
Vol. 2, No. 6, 2010, pp. 297-305
MultiCraft
© 2010 MultiCraft Limited. All rights reserved
Level shifter for low power applications with body bias technique
Manoj Kumar1*, Sandeep K. Arya2 and Sujata Pandey3
1*
2
Department of Electronics & Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar, INDIA
Department of Electronics & Communication Engineering, Guru Jambheshwar University of Science & Technology, Hisar, INDIA
3
Department of Electronics & Communication Engineering, Amity University, Noida, INDIA
*
Corresponding Author: e-mail: manojtaleja@yahoo.com, Tel +91-01662-263547, Fax. +91-01662-276240
Abstract
In present work three new designs of level shifter in 0.35µm technology using body bias approach have been presented. The
level shifters, namely conventional type-I, conventional type-II and contention mitigated have been improved by varying the
reverse body bias from 0.1V to 0.5 V. Circuits have been simulated in Spice with TSMC0.35 process technology. Output level
of 3.3V has been obtained with input pulse of 1.6V. Modified conventional type-I level shifter shows minimum power
consumption of 90.1250pW as compared to 498.33pW for conventional type-I. Further, modified conventional type-II gives
minimum power of 480.28pW as compared to 3479pW with existing circuit. Third proposed circuit namely modified contention
mitigated level shifter (CMLS) show minimum power consumption of 85.52pW as compared to 493.73pW for circuit without
modifications. Simulation results show that proposed circuits are able to shift 1.6V to 3.3V with reduced power consumption
with little conciliation in delay.
Keywords: Body bias, CMOS, level shifter, leakage current and power consumption.
1. Introduction
With the rapid growth in high speed computation and battery...