Introduction to microprocessors
Von Neumanna architecture
CPU
ROM
RAM
I /O
Address bus Data bus Control bus /MEMR, /MEMW, /IOR, /IOW
16 8
Address and data
• • • • • 16 - bit address bus – 216=65536≈64k 20 - bit address bus → 1M (220) 24 - bit address bus → 16M (224) 32 - bit address bus → 4G (232) 8/16/32 - bit data bus – 8/16/32 - bit processor
Address map
0000 16k/4M 4000H 16k/4M 64k, 16M 16k/4M C000H C00000H 16k/4M FFFFH FFFFFFH 64k 16M 8000H 800000H 400000H 000000
Von Neumann architecture
• Common program and data memory • Common program and data bus • Sequential instruction and data access
Harvard’s architecture
Program memory addr. P R Data memory addr.
Program memory
CPU
Data memory
Program (instructions) K
N
Data
Harvard’s architecture
• • • • • Independent program and data memories 2 address buses 2 data buses Parallel access for instruction and data Pipeline mechanism
Procesory RISC i CISC
• • • • • • Reduced Instruction Set Computers Complex Instruction Set Computer CISC ↔ Von Neumann’s arch. RISC ↔ Harvard’s arch. Pipeline mechanism Simultaneous execution and fetching the next instruction
Addressing modes
• Way of defining the position of the operand in the memory • The more addressing modes, the better the microprocessor • Same instructions with different addressing modes • Direct and indirect addressing modes
Addressing modes
100H
instruction
ADD 200H
100H
Instruction
ADD 200H I
200H
Indirect addr.
300H
200H
operand
300H
operand
Addressing modes
• Register addressing (for registers only, e.g. CLA, INC) • Indexed addressing (index register) • Indexed with offset (index and offset registers) • Immediate (operand hidden in the instruction body)
Indexed addressing with offset
instruction Index
+
Adres operand
Offset
+/-
Address = Index ± offset
CPU – Central Processor Unit
Address MAR Memory Address Register...