STATS ChipPac Ltd
Senior / IE Engineer with Wafer Fab Experience
Responsible for Capacity Planning, Technical IE, Cost Engineering & Technical Standards.
• Capacity planning
Capacity resource planning / optimization.
Capacity analysis and commit on monthly forecast, upsides, capital expenditure (CAPEX)
projection, headcount projection.
Capacity scenario (What If) analysis.
Budgeting / planning on capital expenditure (CAPEX) requirement.
Capital Request Form (CRF) justification.
• Technical IE
Goods flow & handling analysis such as: cycle time, layout.
Shop-floor improvement projects.
Define / setup / update Technical standard such as: material consumptions, equipment -Unit per Hour (UPH) by process, equipment efficiency lost (component breakdown), headcount manning ratio on Manufacturing Specialist.
Efficiency improvement such as: Process rationalization, Waste elimination.
System and automation competency such as VBA.
Productivity improvement / Cost reduction opportunities.
Assist plant in cost reduction computation methodology.
Support Finance in Cost modeling
• Masters / Degree in Industrial Engineering or its equivalent.
• At least 2 years’ of Industrial Engineering working experience in semiconductor environment.
• Experience in Front End Semiconductor is an added advantage.
Applicants should be Malaysian, Singaporean citizens or hold relevant residence status.
Victor Siow Yuen Tien’s Experience
(Public Company; INTC; Semiconductors industry)
2009 — Present (1 year )
Project Management: Early Involvement Team for New Product (IE)
Conducts time studies on process equipments for entire new product line. (Assembly & Test). Established equipment capacity modeling and perform standard capacity analysis. Established short term and...