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City University of Hong Kong
Department of Electronic Engineering
EE5430
Advanced CMOS Technology
Laboratory Report
Short-Channel Effect on Threshold Voltage
1. Plot the output characteristics, i.e. Ids versus Vds as a variable.
2. Plot Ids versus Vgs, determine the threshold voltage of the transistor with Vds as a variable.
3. Repeat 1-2 for channel length L = 0.18, 0.35, 0.5, 0.8, 1.0, 1.5, 2 um
Ids versus Vds as a variable ( L=0.18um)
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Ids versus Vds as a variable ( L=0.35um)
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Ids versus Vds as a variable (L=0.5um)
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Ids versus Vds as a variable (L=0.8um)
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Ids versus Vds as a variable (L=1.0um)
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Ids versus Vds as a variable (L=1.5um)
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Ids versus Vds as a variable (L=2um)
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Ids versus Vgs as a variable (L=0.18um)
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Ids versus Vgs as a variable (L=0.35um)
[pic]
Ids versus Vgs as a variable (L=0.5um)
[pic]
Ids versus Vgs as a variable (L=0.8um)
[pic]
Ids versus Vgs as a variable (L=1.0um)
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Ids versus Vgs as a variable (L=1.5um)
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Ids versus Vgs as a variable (L=2um)
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4. Plot the threshold voltage versus L.
|Channel Length (um) |Threshold Voltage (V) |
|0.18 |0.5 |
|0.35 |0.6 |
|0.5 |0.7 |
|0.8 |0.7 |
|1.0 |0.75 |
|1.5 |0.75 |
|2 |0.75 |
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5. Determine the drain induced barrier lowering for different channel lengths using
DIBL = [pic]
|Channel Length (um)...